What Will I Learn?
- Use Vivado to create a simple HDL design
- Sythesize, Implement a design and download to the FPGA
- Create a Microblaze Soft Core Processor
- Understand the fundamentals of the Vivado Design FLow
- Vivado Design Suite 2015.2 or higher
- Basic Knowledge of VHDL
- A 7 Series Xilinx FPGA Development Kit (Artix, Kintex or Virtex)
- PC with Internet connection
- Digital Design Experience
- 6 Series FPGA's are not supported in Vivado
Do you want to learn the new Xilinx Development Environment called Vivado Design Suite? Are you migrating from the old ISE environment to Vivado? Or are you new to FPGA's? This course will teach you all the fundamentals of the Vivado Design Suite in the shortest time so that you can get started developing on FPGA's.
Now why should you take this course when Xilinx Official Partners already offer training? Most of their course are held bi-annually which means you will have to wait at most 6 months before starting the basic training. Also these courses can cost over thousands of dollars.
I am an FPGA Designer with a Masters Degree in Electronic Engineering. I have over 7300 students on Udemy. This course is designed to help you design, simulate and implement HDL code in Vivado through practical and easy to understand labs. You will learn all the fundamentals through practice as you follow along with the training. Together we will build a strong foundation in FPGA Development with this training for beginners. This Course will enable you to:
- Build an effective FPGA design.
- Use proper HDL coding techniques
- Make good pin assignments
- Set basic XDC constraints
- Use the Vivado to build, synthesize, implement, and download a design to your FPGA.
After Completing this Training, you will know how to:
- Design for 7 series+ FPGAs
- Use the Project Manager to start a new project
- Identify the available Vivado IDE design flows (project based)
- Identify file sets such as HDL, XDC and simulation
- Analyze designs by using Schematic viewer, and Hierarchical viewer
- Synthesize and implement a simple HDL design
- Build custom IP cores with the IP Integrator utility
- Build a Block RAM (BRAM) memory module and simulate the IP core
- Create a microblaze processor from scratch with a UART module
- Use the primary Tcl Commands to Generate a Microblaze Processor
- Describe how an FPGA is configured.
This course only costs less than 1% of the Official XIlinx Partner Training Courses which has similar content. Not only will you save on money but you will save on Time. Similar courses usually run over 2 days. This course, however, you will be able to complete in under an hour, depending on your learning speed.
You will receive a verifiable certificate of completion upon finishing the course. We also offer a full Udemy 30 Day Money Back Guarantee if you are not happy with this course, so you can learn with no risk to you.
See you inside this course.
- Digital designers who have a working knowledge of HDL (VHDL) and who are new to Xilinx FPGAs
- Existing Xilinx ISE users who have no previous experience or training with the Xilinx PlanAhead suite and little or no knowledge of Artix-7, Kintex-7 or Virtex-7 devices.
- Engineers who are already familiar with Xilinx 7-series devices
- Designers who are already using Vivado for design should not take this course unless they are struggling with the basics.
- Take this course if you want save $2200 in training costs of similar training material
I am the founder of Augmented Startups and I also hold a Masters Degree in Electronic Engineering. With over 43'000+ students on Augmented AI Bootcamp, and over 60'000 subscribers on YouTube, I teach the latest topics on Artificial Intelligence and Augmented Reality. Together with Geeky Bee AI, we will act as mentors through helping you build or grow your expertise, we look forward to having you!
Start1. Introduction to the Vivado Course (2:22)
Start2. How to Download and Install Xilinx Vivado Design Suite (6:03)
Start3. Introduction to the Vivado Design Suite Interface and Creating a New Project (7:12)
Start4. Coding and Simulating Simple VHDL in Vivado (7:51)
Start5. Implementation of VHDL Design in Vivado and IO Pin Planning (9:11)
Start6. Downloading the Bitstream to the FPGA (1:28)
Start7. Learn VHDL by Example (3:43)
Start8. Design a Block RAM in IP Configurator (7:01)
Start9. Simulating BRAM memory IP in VivadoMB (5:15)
Start10. Creating MicroBlaze in Vivado IP Configurator (10:09)
Start11. Generating a Microblaze using TCL commands in Vivado (3:45)
Start12. Conclusion to the Vivado Course (4:57)